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It is given that:
when Enable input=1 then C'=0, & input D=0 then R=1.
anyone of input 1 in NOR gate=1, the output Q=0.Therefore, Q'=1
When input D=1, D'=0 & another input C'=0 then S=1.
anyone of input 1 in NOR gate=1; the output Q'=1,Therefore, Q=0
Hence, from the above discussion, it is clear that the above circuit will perform as a D-Latch.